RESSL is an acronym that stands for (Read Evaluate Start Sequence Loop) and is a system inspired by the Lisp REPL (Read Evaluate Print Loop) providing an iterative environment in SystemVerilog to launch UVM-based sequences.
It includes a command line interpreter (Read-Evalue) and an API to create an start UVM sequences.
More details are provided in the paper “RESSL UVM Sequences to the Mat” presented at the SNUG Conference in March 2015 in San Jose.